A transceiver is commonly used in communication systems, and the performance of a transceiver highly depends on the accuracy of a clock generator inside the transceiver. Particularly for electronic communication products used in the applications of wireless local area network (WLAN), ultra-wideband (UWB), mobile or entertainment systems, high communication quality, high data-transmission rate and more operation bands are required. Therefore, a phase-locked loop (PLL) circuit with a relatively large tuning range is generally used.
Please refer to FIG. 1 which illustrates a conventional PLL circuit. The PLL circuit 101 includes a phase/frequency detector (PFD) 1010, a charge pump 1011, a loop filter 1012 and a voltage control oscillator (VCO) module 1013. The VCO module 1013 generates an output clock signal with a certain frequency in response to a control voltage for external circuits (not shown). The outputted clock signal is fed back to the PFD 1010 to be processed with a reference clock signal. The PFD 1010 then generates a signal indicating a phase/frequency difference between the reference clock signal and the outputted clock signal. Afterwards, the signal is converted into a control voltage through the charge pump 1011 and loop filter 1012 for controlling the VCO module 1013 to generate the clock signal accurately.
The clock signal generated by the above clock generator is applicable to demodulating a data signal received by a modern electronic communication product. The VCO module 1013 plays an important role in the demodulation process. Generally, a plurality of VCOs with somewhat overlapping operational frequencies for the VCO module 1013 are used for covering a wide tuning range. The inclusion of the plural VCOs complicates the circuitry, occupies considerable chip area and consumes power.